 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| PI6C2502 2 Buffer PI6C2502 Reference Clock Signal V 210987651098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 43212 10987621098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 54321 210987651098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 43212 Phase-Locked Loop Clock Driver Product Features * High-Performance Phase-Locked-Loop Clock Distribution for Networking, * Synchronous DRAM modules for server/workstation/ PC applications * Allows Clock Input to have Spread Spectrum modulation for EMI reduction * Zero Input-to-Output delay * Low jitter: Cycle-to-Cycle jitter 100ps max. * On-chip series damping resistor at clock output drivers for low noise and EMI reduction * Operates at 3.3V VCC * Wide range of Clock Frequencies up to 80 MHz * Package: Plastic 8-pin SOIC Package (W) Product Description The PI6C2502 features a low-skew, low-jitter, phase-locked loop (PLL) clock driver. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. Application If a system designer needs more than 16 outputs with the features just described, using two or more zero-delay buffers such as PI6C2509Q, and PI6C2510Q, is likely to be impractical. The device-to-device skew introduced can significantly reduce the performance. Pericom recommends the use of a zero-delay buffer and an eighteen output non-zero-delay buffer. As shown in Figure 1, this combination produces a zero-delay buffer with all the signal characteristics of the original zero-delay buffer, but with as many outputs as the non-zero-delay buffer part. For example, when combined with an eighteen output non-zero delay buffer, a system designer can create a seventeen-output zero-delay buffer. Logic Block Diagram Product Pin Configuration CLK_IN FB_IN AVCC PLL CLK_OUT FB_OUT AGND FB_OUT 1 2 3 4 CLK_OUT VCC 8-Pin W 8 7 6 5 CLK_IN AVCC GND FB_IN Feedback Zero Delay CLK_OUT 18 Output Non-Zero Delay Buffer 17 Figure 1. This Combination Provides Zero-Delay Between the Reference Clocks Signal and 17 Outputs 1 PS8382B 03/20/02 PI6C2502 Phase-Locked Loop Clock Driver 210987651098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 43212 210987651098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 43212 Pin Functions Pin Name CLK_IN FB_IN FB_O UT CLK _O UT AVC C AGND VC C GND Pin Numbe r 8 5 2 3 7 1 4 6 Type I I O O Power Ground Power Ground De s cription Reference Clock input. CLK_IN allows spread spectrum clock input. Feedback input. FB_IN provides the feedback signal to the internal PLL. Feedback output FB_OUT is dedicated for external feedback. FB_OUT has an embedded series- damping resistor of the same value as the clock outputs CLK_OUT. Clock outputs. These outputs provide low- skew copies of CLK_IN. Each output has an embedded series- damping resistor. Analog power supply. AVC C can be also used to bypass the PLL for test purposes. When AVC C is strapped to ground, PLL is bypassed and CLK_IN is buffered directly to the device outputs. Analog ground. AGND provides the ground reference for the analog circuitry. Power supply. Ground. DC Specifications (Absolute maximum ratings over operating free-air temperature range) Symbol VI VO IO_DC Power TSTG Parame te r Input voltage range Output voltage range DC output current Maximum power dissipation at TA = 55oC in still air Storage temperature 65 M in. 0.5 M ax. VCC +0.5 100 1.0 150 Units V mA W oC Note: Stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. Parame te r ICC CI CO Te s t Conditions VI = VCC or GND; IO = 0(1) VI = VCC or GND VO =VCC or GND VCC 3.6V 3.3V M in. Typ. M ax. 10 Units A pF 4 6 Note: 1. Continuous Output Current 2 PS8382B 03/20/02 PI6C2502 Phase-Locked Loop Clock Driver 210987651098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 43212 210987651098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 43212 Recommended Operating Conditions Symbol VC C VIH VIL VI TA Supply voltage High level input voltage Low level input voltage Input voltage O perating free- air temperature 0 0 Parame te r M in. 3.0 2.0 0.8 VC C 70 C M ax. 3.6 V Units Electrical Characteristics Symbol IO H IO L (Over recommended operating free-air temperature range Pull Up/Down Currents, VCC = 3.0V) Parame te r Pull- up current Pull- down current Condition VO U T = 2.4V VO U T = 2.0V VO U T = 0.8V VO U T = 0.55V M in. M ax. -18 -30 Units 25 17 mA AC Specifications Timing Requirements Symbol FCLK DCYI Clock frequency Input clock duty cycle (Over recommended ranges of supply voltage and operating free-air temperature) Parame te r M in. 25 40 M ax. 80 60 1 Units MHz % ms Stabilization Time after power up Switching Characteristics Parame te r tphase error without jitter Jitter, cycle- to- cycle Skew at 100 MHz and 66 MHz Duty cycle tr, rise- time, 0.4V to 2.0V tf, fall- time, 2.0V to 0.4V (Over recommended ranges of supply voltage and operating free-air temperature, CL =30pF) From (Input) CLK _IN at 100MHz and 66MHz At 100 MHz and 66 MHz CLK _O UT or FB_O UT To (Output) FB_IN CLK _O UT CLK _O UT or FB_O UT VC C = 3.3V 0.3V, 0-70C M in. 150 100 Typ. M ax. +150 +100 200 45 55 1.0 1.1 Units ps % ns CLK _O UT or FB_O UT Note: These switching parameters are guaranteed by design. 3 PS8382B 03/20/02 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2502 Phase-Locked Loop Clock Driver Layout and Schematic Guidelines Introduction Because of todays high-speed design demands, board designers must have extensive knowledge concerning transmission line effect, EMI, and crosstalk. They also need to understand board materials, signal and power stacking, connectors, cables, vias, and trace dimensions. Pericom Semiconductor Corporation offers an extensive line of high-speed clock products for desktop, notebook, set top boxes, information device, servers, and workstations. To make high-speed chips function properly, a designer needs to rely on accurate schematics and layout guidelines. This application note focuses on Pericoms PI6C2502 Zero- Delay Clock Buffer, presenting schematics and layout guidelines for the chip. Also listed are some decoupling guidelines that are important for this chips varied applications. Decoupling Capacitors Every printed circuit board needs large bypass capacitors to balance the inductance of the power-supply wiring. These capacitors have some lead inductance that increase as the frequency goes higher, which is why it is very important to place the capacitors as close as possible to the VCC and Ground Pins on the Chip. To reduce the series lead inductance effect, avoid the following: 1. Long traces larger than 0.01 inch between capacitor pad and via 2. Use of capacitors other than surface mount 3. Via holes less than 0.035-inch diameter Pericoms clocks use high-precision, integrated analog PLL that can be effected by the power supply and ground pins. Noise on these two pins can dramatically increase skew and output jitter. To minimize these problems, connect a 4.7F, a 220nF , and a 2.2nF capacitor to the digital supply pin. Also use one 4.7F , one 220nF, and one 2.2nF capacitor on the analog supply pin. Connect the other side to the analog ground pin. Place a 10F capacitor from the main power island to the power plane that is supplied to the clock chip. Use high-quality, low ESR, ceramic surface-mount capacitors. Stacking At low speeds, currents follow the least resistance path, but at high speeds current follows the least inductance path. The lowest inductance return path lies directly under the signal conductor. Application Note This location minimizes the total loops needed between the outgoing and returning paths. That is why it is important to separate the signal layers by ground planes if possible. Also avoid totally cutting part of the ground plane to be used for a signals path. That is totally unacceptable, because it will increase crosstalk considerably and does not provide a clean return to those signals. Also use lower trace impedance because it lowers undershoot and overshoot. Always use FR-4 material for board fabrication. Use 4- layer stack-up arrangement. Make sure you have a signal layer that is followed by the ground layer, then a power layer, and finally the second signal layer. Please see Figure 1 below. Z = 60 Ohms 5 mils 47 mils 5 mils Z = 60 Ohms Primary Signal Layer (1/2 oz. cu.) PREPREG CORE Ground Plane (1 oz. cu.) Power Plane (1 oz. cu.) PREPREG Secondary Signal Layer (1/2 oz. cu.) Total Board Thickness = 62.6 Figure 1: Four-Layer Board Stack-up Clock routing and spacing To minimize crosstalk on the clock signals, use a minimum of 0.014-inch spacing between clock traces and others. If you have to use serpentine to match trace lengths on similar chips, make sure that you have at least 0.018-inch spacing for serpentines. Please see Figure 2 below. 0.014" 0.018" Clock Figure 2: Clock Trace Spacing Guidelines 4 PS8382B 03/20/02 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2502 Phase-Locked Loop Clock Driver Schematic Drawing INPUT_CLOCK 25-150 MHZ PI6C2502 AGND FB_OUT CLK_IN 1.5H AVCC 4.7F .22F .002F Board AVCC CLK_OUT 3.3V Power Supply .22F GND FB_IN 1.5H 4.7F .002F VCC 5-12pF Feedback Capacitor Decoupling Capacitors Series Terminating Resistor Clock Chip Layout PI6C2502 AVCC Island for PI6C2510 AGND AVCC L CLK_IN C C C AGND AGND AGND FB_OUT R C GND C C L VCC CLK_OUT GND FB_IN CFB GND Use Wider Traces for Ground and Power (0.034-inch width, 0.1-inch pitch) Legend: GND AGND VCC AVCC R C L CFB = = = = = = = = Via to Digital Ground Via to Analog Ground Via to 3.3V Digital Power Via to 3.3V Analog Power Termination Resistor 12-32 Decoupling Capacitor Inductor Feedback Capacitor 5 PS8382B 03/20/02 Ordering Information Orde ring Code PI6C2502W Package Name W8 Package Type 8- pin 150- mil SOIC Ope rating Range Commercial 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6C2502 Phase-Locked Loop Clock Driver Package Mechanical Information Plastic 8-pin SOIC Package 8 .149 .157 3.78 3.99 4.80 .189 5.00 .196 1 .016 REF .026 0.406 0.660 .053 .068 1.35 1.75 .0099 .0196 0.25 x 45 0.50 SEATING PLANE 0-8 .0075 .0098 0.40 .016 1.27 .050 .2284 .2440 5.80 6.20 0.19 0.25 .050 BSC 1.27 .013 .020 0.330 0.508 X.XX X.XX .0040 0.10 .0098 0.25 DENOTES DIMENSIONS IN MILLIMETERS Pericom Semiconductor Corporation 2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com 6 PS8382B 03/20/02 |
Price & Availability of PI6C2502
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |